module enqueueRamDeMuxer16 (
    input wire clk,
    input wire rst,
    input wire [15:0] enqueue_sucess,
    input wire enqueue_en_in,
    input wire [5:0] enqueue_priority_in,
    input wire [9:0] enqueue_value_in,
    input wire [5:0] enqueue_port_in,
    output reg [15:0] enqueue_en_out,
    output reg [5:0] enqueue_priority_out [0:15],
    output reg [9:0] enqueue_value_out [0:15]
);

    integer i;

    always @(posedge clk) begin
        if (rst) begin
            enqueue_en_out <= 16'h0000;
            for (i=0; i<16; i=i+1) begin
                enqueue_priority_out[i] <= 0;
                enqueue_value_out[i] <= 0;
            end
        end
        else begin
            if (enqueue_sucess[enqueue_port_in]) begin
                enqueue_en_out <= 16'h0000;
                for (i=0; i<16; i=i+1) begin
                    enqueue_priority_out[i] <= 0;
                    enqueue_value_out[i] <= 0;
                end
            end
            else begin
                if (enqueue_en_in) begin
                    enqueue_en_out <= (1 << enqueue_port_in);
                    enqueue_priority_out[enqueue_port_in] <= enqueue_priority_in;
                    enqueue_value_out[enqueue_port_in] <= enqueue_value_in;
                end
                else begin
                    enqueue_en_out <= 16'h0000;
                end
            end
        end
    end
    
endmodule